1. Field of the Invention
The present invention relates to a ferroelectric memory device having a test memory cell.
2. Description of the Related Art
A FeRAM (ferroelectric random access memory) is a known type of semiconductor memory. The FeRAM uses a function of the ferroelectric layer for reversing an electric field by an intrinsic polarization and for retaining the electric field. A structure of the ferroelectric memory device is shown in the Japanese language references K. Shimizu: “Low-power High-speed LSI Circuits & Technology” Realize Co., Ltd., Inc. p 231–250 Jan. 31, 1998 and T. Kawai: “Non-volatility IC memory—All the FRAMs” Kogyo Chosakai Co., Ltd., Inc. p 29–37 Jul. 7, 1996. A 1T/1C type ferroelectric memory device and a 2T/2C type ferroelectric memory device are known as shown in these references.
In the 1T/1C type ferroelectric memory device, one transistor and one ferroelectric capacitor form one memory cell. A stored data in the memory cell is read by comparing between a stored voltage and a reference voltage.
In the 2T/2C type ferroelectric memory device, two transistors and two ferroelectric capacitors form one memory cell. Each capacitor stores complementary data of “1” or “0” respectively. A stored data in the memory cell is read by comparing the voltage of the ferroelectric capacitors.
An operation test of a semiconductor memory device is known in which a determination is made as to whether the memory device can store data of “1” and “0” correctly. In this operation test, the testing equipment writes testing data to all the memory cells, and then the written data is read from all the memory cells. The test is performed by comparing the testing data and the written data.
Recently, high-capacity ferroelectric memory devices have been developed in which the number of memory cells included in one ferroelectric memory chip is increased. If the ferroelectric memory chip includes at least one defective cell, the ferroelectric memory chip is judged as a defective product. As a result, increasing a number of the memory cells in the ferroelectric memory device decreases productivity.
A technique using redundancy memory cells for increasing productivity is known. In this technique, a redundancy memory array is added to the memory cell array. In the ferroelectric memory device with the redundancy memory cells, if the ferroelectric memory device includes a defective cell, a memory cell column (or a memory cell row) which includes the defective cell is changed to a redundancy memory cell column (or a redundancy memory cell row) in the redundancy memory cell array. As a result, the ferroelectric memory device which includes the defective memory cell can be shipped as a non-defective product.
However, adding the redundancy memory cell array causes an increase in the number of the memory cells in the ferroelectric memory chip. Therefore, the testing time for testing the ferroelectric memory cells is increased.
Further, in the operating test for changing the defective memory cell array to the redundancy memory cell array, it is necessary to detect an address of the defective memory cell. Therefore, the conventional testing equipment for the ferroelectric memory device must store a lot of test results and detect the address of the defective memory cell from the test results. As a result, the structure and the control of the testing equipment for the ferroelectric memory device are complicated and price of the testing equipment is high.
A technique for detecting the address of a defective DRAM memory cell is described in Japanese Patent Laid-Open No 10-144091. The reference describes using a refresh feature of the DRAM. However, the FRAM does not have a refresh feature, and therefore, it is difficult to apply this technique to the FRAM.